1. Field of the Invention
The present invention relates to a logic circuit, and particularly to a logic circuit employing previously prepared macrocells to enable the logic circuit to be tested easily and to enhance the feasibility of testing such a logic circuit.
2. Description of the Prior Art
In recent years, LSIs (Large Scale Integrated Circuits) based on the macrocell system have been used. These LSIs are custom LSIs. The macrocell system uses macrocells each of which is a circuit block comprising a plurality of elements such as transistors, resistors and capacitors to realize a predetermined function such as RAM and ALU operation. The macrocells are prepared in advance and registered in, for instance, a data base. The macrocells thus prepared are arranged and interwired manually or with a CAD to design and form an LSI. Compared to other conventional designing method, the macrocell system can greatly reduce the developing period and developing costs of a LSI.
As a reasonable test for a logic circuit such as an LSI, a method of supplying test data to the logic circuit and comparing the output from the logic circuit with an expected value is generally used. An example of this sort of method is the LSSD (Level Sensitive Scan Design) method. This method of testing an integrated circuit with this method will now be explained.
In testing the integrated circuit, all flip-flops (FFs) in the integrated circuit are controlled to form one continuous shift register. Input test data from a test data generating unit is passed through the shift register and supplied to a combinational logic circuit in the integrated circuit, and this combinational logic circuit is controlled to execute one cycle of operation.
An output signal from the combinational logic circuit is latched by the shift register, output from the integrated circuit via a scan signal output terminal, and compared with an expected value to judge whether or not the integrated circuit has operated according to a predetermined function.
Conventionally, the logic circuit designed and formed according to the macrocell system is tested as a whole by using, for instance, the LSSD method.
Since the circuit is tested as a whole, it is difficult to reuse test data already prepared for the individual macrocells, and so test data for the logic circuit as a whole must be newly prepared.